1. Field of the Invention
This invention relates to a sustaining pulse generator of a plasma display panel, and more particularly to a sustaining pulse generator of a plasma display panel that is capable of simplifying a circuit configuration thereof.
2. Description of the Related Art
Generally, a plasma display panel (PDP) radiates a fluorescent body by an ultraviolet with a wavelength of 147 nm generated during a discharge of He+Xe or Ne+Xe gas to thereby display a picture including characters and graphics. Such a PDP is easy to be made into a thin-film and large-dimension type. Moreover, the PDP provides a very much improved picture quality owing to a recent technical development.
Such a PDP drives one frame, which is divided into various sub-fields having a different emission frequency, so as to realize gray levels of a picture. Each sub-field is again divided into a reset interval for uniformly causing a discharge, an address interval for selecting the discharge cell and a sustaining interval for realizing the gray levels depending on the discharge frequency. When it is intended to display a picture of 256 gray levels, a frame interval equal to 1/60 second (i.e. 16.67 msec) in each discharge cell is divided into 8 sub-fields SF1 to SF8. Each of the 8 sub-fields SF1 to SF8 is divided into a reset interval, an address interval and a sustaining interval.
The reset interval and the address interval of each sub-field are equal every sub-field. A voltage difference between a data electrode and a scanning electrode causes an address discharge to select cells. The sustaining interval increases in proportion of 2n (wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field. The gray levels necessary for displaying a picture can be realized by controlling the sustaining discharge frequency of the sustaining interval in each sub-field. The sustaining discharge is caused by a sustaining pulse of high voltage alternately applied to the scanning electrode and a sustaining electrode.
Referring to FIG. 1, a sustaining pulse generator for generating a sustaining pulse of a PDP according to the related art includes an AC input unit 1 supplying AC voltage, a Power Factor Correction PFC unit 10 improving the power factor of the voltage applied from the AC input unit 1 and eliminating harmonics, a DC/DC converter 20 converting DC voltage generated at the PFC unit 10 into square wave and at the same time transforming it, and a sustaining pulse supplier 30 applying the square wave of the transformed DC voltage to a PDP panel 40.
The PFC unit 10 controls input current from the AC input unit to generate sine waves with the same phases, improve power factor and at the same time eliminate harmonics noise.
To this end, the PFC unit 10, as in FIG. 2, includes a rectifying circuit 12 rectifying the AC inputted from the AC input unit 1 to DC, and a power factor correction circuit 14 improving the power factor of the DC rectified at the rectifying circuit 12.
The rectifying circuit 12 includes a first diode DF1 and a second diode DF2 arranged in a full bridge type and being forward biased during a positive (+) half period of the inputted AC, and a third diode DF3 and a fourth diode DF4 being forward biased during a negative (−) half period. The rectifying circuit 12 does full wave rectification to the AC inputted from the AC input unit 1 and stores the produced DC at a smoothing capacitor 2C.
The power factor correction circuit 14 includes a coil 2L being charged with a current component of the DC stored at the smoothing capacitor 2C of the rectifying circuit 12, a first transistor 2T1 installed between the coil 2L and the rectifying circuit 12 and switching for the current component of the DC to be stored at the coil 2L, and a first capacitor Cdc1 being charged with a voltage component of the DC applied from the smoothing capacitor 2C by switching of the first transistor 2T1.
When a control signal (not shown) turns on the first transistor 2T1, there is a loop formed between the smoothing capacitor 2C, the first transistor 2T1 and the coil 2L and the current component of the DC is stored at the coil 2L. Further, when the control signal (not shown) turns off the first transistor 2T1, the voltage component of the DC stored at the smoothing capacitor 2C is stored at the first capacitor Cdc1.
There is a diode Do installed between the coil 2L and the first capacitor Cdc1 in the power factor correction circuit 14 for shutting off reverse current from the first capacitor Cdc1 to the coil 2L.
Referring to FIG. 3, the DC/DC converter 20 includes a bridge switch 22 connected to both ends of the first capacitor Cdc1 of the PFC unit 10, a center tap transformer 3T transforming the voltage applied by the switching of the bridge switch 22, a second capacitor 3C2 and a first inductor 3L1 connected in series between the center tap transformer 3T and the bridge switch 22, a full wave rectifier 24 connected to a secondary winding of the center tap transformer 3T and rectifying the voltage induced to the center tap transformer 3T, a smoothing capacitor 3Cdc2 being charged with the voltage outputted from the full wave rectifier 24, and the second inductor 3L2 arranged in series between the smoothing capacitor 3Cdc2 and the full wave rectifier 24.
The bridge switch 22 consists of a first to a fourth switches 3Q1, 3Q2, 3Q3 and 3Q4 arranged in a full bridge type at both ends of the first capacitor Cdc1.
The first and third switches 3Q1 and 3Q3 are connected in parallel with one end of the first capacitor Cdc1, and the second and fourth switches 3Q2 and 3Q4 are connected in parallel with the other end of the first capacitor Cdc1. Herein, the first to fourth switches 3Q1, 3Q2, 3Q3 and 3Q4 are Field Effect Transistors FET.
There are a first node 3N1 connected to the first and fourth switches 3Q1 and 3Q4, and a second node 3N2 connected to the second and third switches 3Q2 and 3Q3. The first node 3N1 is connected to the upper end of a primary winding of the center tap transformer 3T through the second capacitor 3C2 and the first inductor 3L1, and the second node 3N2 is connected to the lower end of the primary winding of the center tap transformer 3T. The bridge switch 22 converts the voltage applied from the first capacitor Cdc1 by the alternate switching of the first to fourth switches 3Q1, 3Q2, 3Q3 and 3Q4 to apply to the primary winding of the center tap transformer 3T.
The second capacitor 3C2 is a DC blocking capacitor for preventing a current with a DC component applied to the center tap transformer 3T via the bridge switch 22.
The first inductor 3L1 is a resonant coil for eliminating switching loss of the first to fourth switches 3Q1, 3Q2, 3Q3 and 3Q4 of the bridge switch 22.
The center tap transformer 3T insulates the primary winding and the secondary winding and converts the input voltage. In other words, the center tap transformer 3T transforms the voltage applied from the primary winding to the secondary winding by a turn-ratio between the primary winding and the secondary winding. The center tap transformer 3T induces the voltage from the primary winding to the secondary winding by the turn-ratio between the primary winding and the secondary winding The one end of the primary winding of the center tap transformer 3T is connected to the first inductor 3L1, the other end of the primary winding to the second node 3N2.
The full wave rectifier 24 includes a first diode 3D1 arranged between both ends of the secondary winding of the center tap transformer 3T and a second diode 3D2 arranged between the first diode 3D1 and a positive (+) terminal of the center tap transformer 3T in order to rectify the AC pulse induced to the secondary winding of the center tap transformer 3T.
The second diode 3D2 rectifies the positive square wave induced between the positive (+) terminal and a center tap of the secondary winding and applies it to the smoothing capacitor 3Cdc2 through the second inductor 3L2. The first diode 3D1 rectifies the negative square wave induced between the center tap and the negative (−) terminal of the secondary winding and applies it to the smoothing capacitor 3Cdc2 through the second inductor 3L2. Herein, the second inductor 3L2 acts to smooth the square wave, which is rectified by the first and second diodes 3D1 and 3D2, to DC.
The DC/DC converter 20 has the same circuit configuration as an ordinary DC/DC converter, and the voltage stored at the smoothing capacitor 3Cdc2 of the DC/DC converter 20 is applied to the sustaining pulse supplier 30.
The sustaining pulse supplier 30 includes a third capacitor 3C3 for eliminating ripple of the voltage applied from the smoothing capacitor 3Cdc2, and a fifth switch 3Q5 and a sixth switch 3Q6 connected in parallel with both ends of the third capacitor 3C3.
The third capacitor 3C3 is connected in parallel with the smoothing capacitor 3Cdc2 of the DC/DC converter 20. The third capacitor 3C3 compensates the ripple generated by line resistance when the voltage is applied from the smoothing capacitor 3Cdc2.
The fifth and sixth switches 3Q5 and 3Q6 switches to allow the DC voltage stored at the third capacitor 3C3 to be applied to a panel capacitor Cp. Herein, the fifth and sixth switches 3Q5 and 3Q6 are Field Effect Transistors FET.
In the sustaining pulse generator according to the related art, after the first switch 3Q1 is turned on by the switching control signal (not shown), the second switch 3Q2 is turned on so that the voltage of the first capacitor Cdc1 flows via the first switch 3Q1, the second capacitor 3C2, the first inductor 3L1, the primary winding of the center tap transformer 3T and the second switch 3Q2. Accordingly, the voltage stored at the first capacitor Cdc1 is made to induce a positive voltage +SUS to the secondary winding of the center tap transformer 3T. The positive voltage +SUS induced to the secondary winding is rectified into a positive sustaining pulse by the second diode 3D2 and stored at the smoothing capacitor 3Cdc2 and the third capacitor 3C3 to be applied to the panel capacitor Cp.
Subsequently, the first and second switches 3Q1 and 3Q2 are turned off, then the third switch 3Q3 is turned on by a switching control signal (not shown), then the fourth switch 3Q4 is turned on. With this, the voltage of the first capacitor Cdc1 flows the third switch 3Q3, the primary winding of the center tap transformer 3T, the first inductor 3L1, the second capacitor 3C2, the fourth switch 3Q4. Accordingly, the voltage stored at the first capacitor Cdc1 is made to induce a negative voltage −SUS to the secondary winding of the center tap transformer 3T. The negative voltage −SUS induced to the secondary winding is rectified into a positive sustaining pulse by the first diode 3D1 and applied to the panel capacitor Cp through the smoothing capacitor 3Cdc2 and the third capacitor 3C3.
In this way, because the conventional sustaining pulse generator converts the AC input voltage into the sustaining pulse through the PFC unit 10, the DC/DC converter 20 and the sustaining pulse supplier 30, it increases circuit loss such as conduction loss and switching loss etc in many circuit devices in the course of conversion. In addition, a cost for fabricating the circuit increases due to the complexity of the circuit.